Boolean logic: present inputs versus stored state

Start with a finite model

Boolean logic represents two possible values, commonly written 0 and 1 or false and true. The symbols do not by themselves specify a particular physical voltage. In an abstract logic question, begin with the stated relationship between inputs and output. A truth table lists every possible input combination and the result for each one. With two independent binary inputs, there are four rows; with three, there are eight. AND is true only when both inputs are true. Inclusive OR is true when at least one is true. NOT reverses a value. Exclusive OR, usually called XOR, is true when its two inputs differ. Ordinary conversation sometimes uses “or” ambiguously, so a technical problem must make its intended operation clear.

Combinational logic and memory

A combinational output depends on the current inputs, after any propagation delay has settled. A sequential system also depends on stored state. The distinction is not that one is complicated and the other simple. A large combinational network can implement many decisions without remembering a previous input; a single storage element can introduce state. For an ideal rising-edge-triggered D flip-flop, the stored output takes the D input value at the active rising edge, then holds that value between active edges. This simplified description assumes valid timing and ignores additional controls unless the question specifies them. It is a reasoning model, not a hardware timing specification.

Worked example: simplifying a decision

Let the output be F = A OR (A AND B). Test the four input pairs. If A = 0, the first term is 0 and the second term is also 0, whatever B is. If A = 1, the first term already makes the OR output 1, again whatever B is. Thus F always equals A. This is called the absorption relationship. The table supplies a complete argument because every possible pair has been covered. Notice the reasoning is about logical values: replacing OR with ordinary numeric addition would incorrectly suggest a possible output of 2 when both terms are true.

Worked example: a stored value

Suppose a hypothetical rising-edge D flip-flop starts with Q = 0. D becomes 1 before the first rising edge and remains valid through that edge. Q becomes 1 at the edge. D then changes to 0 while the clock is steady high. In this ideal edge-triggered model, Q stays 1 until the next active rising edge, when it takes the new D value of 0. A combinational buffer driven by D would instead follow the present D value after its delay. The different response between clock edges reveals why a storage element cannot be understood from a present-input table alone. Its previous state and the timing of the updating event matter.

Do not confuse OR and XOR

For input pair 1,1, inclusive OR produces 1 while XOR produces 0. This single row can expose a mistaken identification. For example, a model that selects exactly one of two choices uses different logic from a model that accepts either choice and also permits both. Write the rule in words before assigning a gate name. A second misconception is that a clock being high is the same event as a rising edge. An edge is a transition from low to high; a high level lasts for an interval. Edge-triggered storage and level-sensitive behavior are different models. Use the one explicitly named by the question.

Sources & further reading